Microelectronics Research Development Corporation
KM-807704; Temporal LatchTM SEU Immune RHBD 90nm CMOS 32 Bit RISC SoC
Electronic integrated circuits providing radiation hardening for digital logic architecture
Specifications: 
 
32-Bit RISC CPU 
  • 50 MHz Clock 
  • Based on Open Cores SoC 
  • 256Kx8 Program Space (EDAC Protected) 
  • 16Kx8 Data RAM 
  • 2 x 16650 UARTS Full HW Flow Control/FIFO 
  • 6 x PWM/Counter/Capture (32 bit)  
  • 32 Bidirect GPIO 
  • WDT 
  • I2C Master/Slave 
  • I2C Master 
  • SPI Master with 5 Chip Selects  
  • Firmware Download (SPI) 
  • SPI Bootup External SPI NVM 
  • GCC tool chain
Die  
  • 7mm X 7mm 
  • 406 Total Pins 
  • 248 CMOS Pins 
  • 64 um pad pitch 
  • 50 um X 50 um pad size 

Dual Voltage Supply 1.2V Core and 1.2V to 2.5V I/O
RHBD IBM 9LP 90nm CMOS 
  • Total Ionizing Dose: Within specifications after exposure to greater than 1Mrad(Si). 
  • Single Event Latch Up: Latchup immune to 80 MeV-cm2/mg 
  • SRAM Error Rate: Supports scrubbing program SRAM to obtain desired error rates 
  • Single Event Transient: Implements the Temporal Latch-based flip flops to mitigate transient pulse widths of up to 1ns.
Block Diagram
This effort is sponsored by the Air Force Research Laboratory (AFRL)