Microelectronics Research Development Corporation
KM-805502; Temporal LatchTM SEU Immune RHBD 90nm CMOS 8 Bit RISC System on a Chip (SoC)
Electronic integrated circuits providing radiation hardening for digital logic architecture
  • 50 MHz Clock 
  • Based on Micro-RDC Enhanced Open Cores PIC 
  • Supports 2x96x8 Byte Register Files  
  • 16 bit GPIO 
  • 2 x 16650 UARTS Full HW Flow Control/FIFO 
  • 6 x PWM/Counter/Capture (2 with Interrupt Capability)
  • Watch Dog Timer 
  • External Interrupt
Temporal Latch Technology 
  • SEU Immune by Incorporating Temporal Latch Technology in all Sequential Logic 
Memory Sub Systems 
  • On Chip Internal Register File (2x96x8) 
  • Temporal Latch Based Flip Flops 
  • On Chip 8Kx14bit EDAC Program RAM
  • Bootup from External SPI EEPROM  
  • On Chip ROM for Testing and Bootup 
  • SPI Slave for Firmware Download and Upload to Silicon  
  • Support for 128 Kbytes External SPI Non Volatile Memory 
  • I2C Master/Slave 
  • I2C Master 
  • SPI Master with Multiple Slave Chip Enables 
  • I2C Primary Master 
  • I2C Secondary Master 
  • I2C Slave 
  • SPI Master with 8 Slave Selects 
  • SPI Slave 
  • 5mm X 5mm 
  • 64 um pad pitch 
  • 50 um X 50 um pad size 

Dual Voltage Supply 1.2V Core and 1.2V to 2.5V I/O
Block Diagram
  • Total Ionizing Dose: Within specifications after exposure to greater than 1Mrad(Si) 
  • Single Event Latch Up: Latchup immune to 80 MeV-cm2/mg 
  • SRAM Error Rate: Supports scrubbing program SRAM to obtain desired error rates 
  • Single Event Transient: Implements the Temporal Latch-based flip flops to mitigate transient pulse widths of up to 1ns
This effort is sponsored by the Air Force Research Laboratory (AFRL).